i2c_send/i2c_recv/spi

The SaarCPU has hardware support for serial communication via I²C and SPI. i2c_send sends the accumulator bit by bit, starting with the most significant bit. i2c_recv receives a byte (again starting with the most significant bit), storing it in the accumulator. spi sends and receives one byte at the same time, starting with the least significant bit. Source and destination are the accumulator.

Instruction	Encoding	Semantics	Cycles
i2c_send	10 001 001	see below	12
i2c_recv	10 010 010	see below	12
spi	10 011 011	see below	10

i2c_send

The following steps are executed in the specified order with the I²C/SPI clock as well as SPI_SEND enabled:

1. send $0$ (start bit)
2. send $\mathit{acc}[7]$
3. send $\mathit{acc}[6]$
4. send $\mathit{acc}[5]$
5. send $\mathit{acc}[4]$
6. send $\mathit{acc}[3]$
7. send $\mathit{acc}[2]$
8. send $\mathit{acc}[1]$
9. send $\mathit{acc}[0]$
10. receive acknowledge (should be $0$ but is not checked)
11. send $0$ (stop bit)

The 12th micro instruction in our implementation is used for the instruction fetch.

i2c_recv

The following steps are executed in the specified order with the I²C/SPI clock enabled and SPI_SEND disabled:

1. receive the start bit (should be $0$ but is not checked)
2. receive $\mathit{acc}[7]$
3. receive $\mathit{acc}[6]$
4. receive $\mathit{acc}[5]$
5. receive $\mathit{acc}[4]$
6. receive $\mathit{acc}[3]$
7. receive $\mathit{acc}[2]$
8. receive $\mathit{acc}[1]$
9. receive $\mathit{acc}[0]$
10. send $0$ (acknowledge)
11. ignore stop bit (should be $0$ but is not checked)

The 12th micro instruction in our implementation is used for the instruction fetch.

spi

The following steps are executed in the specified order with the I²C/SPI clock enabled and SPI_SEND disabled:

1. send and receive $\mathit{acc}[0]$
2. send and receive $\mathit{acc}[1]$
3. send and receive $\mathit{acc}[2]$
4. send and receive $\mathit{acc}[3]$
5. send and receive $\mathit{acc}[4]$
6. send and receive $\mathit{acc}[5]$
7. send and receive $\mathit{acc}[6]$
8. send and receive $\mathit{acc}[7]$

Our implementation needs 10 cycles because it needs to transfer the $\mathit{acc}$ to the ALU latch before step 1 and perform the instruction fetch after step 8.