add/adc

The add and add with carry instructions perform the additions as shown in the table below. All flags are updated accordingly.

Instruction	Encoding	Semantics	Cycles
add acc, reg8	01 000 rrr	$\mathit{acc} \gets \mathit{acc} + \mathit{reg8}$	3/41/52
adc acc, reg8	01 001 rrr	$\mathit{acc} \gets \mathit{acc} + \mathit{reg8} + \mathit{CF}$	3/41/52
add acc, imm8	00 000 011 imm8	$\mathit{acc} \gets \mathit{acc} + \mathit{imm8}$	3
adc acc, imm8	00 001 011 imm8	$\mathit{acc} \gets \mathit{acc} + \mathit{imm8} + \mathit{CF}$	3
add ab, reg16	11 10 00 ww	$\mathit{ab} \gets \mathit{ab} + \mathit{reg16}$	7
add reg16, imm8s16	11 10 01 ww imm8	$\mathit{reg16} \gets \mathit{reg16} + \mathit{sext}(\mathit{imm8})$	7

1. 4 cycles for unprefixed add acc, [pi]/adc acc, [pi]
2. 5 cycles for add acc, [pi]/adc acc, [pi] with prefix_a16 (the sequence prefix_a16; add acc, [pi] takes 6 cycles)