RAM and Bootup ROM
The memory unit was mainly developed by Julius Herrmann, Robert Pietsch and Julian Rederlechner. It is in working condition and has been integrated into the final build.
Overview
The memory unit consists of a 16-bit addressable RAM and a 12-bit addressable ROM for the operating system.
RAM and ROM share the same address space where the lowermost 12-bit addresses (0x0000 to 0x0FFF) map to the ROM and the remaining addresses map to the RAM.
Addresses are taken from the current address latch state within the register file.
We implemented the address space mapping by or-ing the uppermost four address bits and feeding the resulting line into the chip select inputs of the RAM and ROM chips.
Schematics and Chip Layout
Inner Workings
| Control Line | Type | Purpose |
|---|---|---|
~MEM_FROM_DBUS | Active Low | Emits the value stored at the address latch state to the data bus. |
~MEM_TO_DBUS | Active Low | Writes the value from the data bus into the RAM at the address latch state. |
We are using a AS6C1008 RAM chip as main system memory and a SST39SF010A-70 flash chip for bootup ROM.
Both chips have tristate in-/outputs which allows us to directly connect them to the data bus.
Because both chips support an address space greater than 16 bits, we fixed superfluous bits on the chips to zero.
As mentioned before, we decided to split the address space such that addresses 0x0000 to 0x0FFF map to the ROM and that addresses 0x1000 to 0xFFFF map to the RAM.
This allows us to use the 4096 addressable ROM bytes for a small operating system, which is why we call the ROM bootup ROM from now on.
Using the lowermost 12-bit addresses for the bootup ROM brings the additional benefit that the OS program can begin at address 0x0000 which simplifies the reset logic significantly.
The remaining address space is used as the main system RAM.
Data flow from the chips to the data bus is managed by the ~MEM_TO_DBUS control line, which toggles the output enable pins of both chips.
We decide between selecting the RAM and ROM chip based on the four most significant address bits:
If and only if all four bits are zero, the bootrom chip is selected, otherwise the main RAM gets selected.
The value stored at the location represented by the address latch state will be emitted to the data bus as long as the ~MEM_TO_DBUS control line is active (low).
Writing to RAM is triggered by the ~MEM_FROM_DBUS control line.
The RAM chip will update the value stored at the location represented by the address latch state to the value on data bus as long as the control line is active (low).
If the address latch holds a value that is mapped to the bootup ROM, the write operation has no effect and will not modify the ROM's state.
Internally, the data bus value will be written into the RAM at the respective location in this case.
This is transparent to the ISA as the written value cannot be retrieved from the RAM due to the ROM mapping.
To save a chip on the memory board, we used the second quad-nor gate in the 74-4002 chip as a not gate by connecting all inputs to the same signal.
Tips for Reproduction
- Laying the cables for the address lines and the data bus tends to get messy quickly as the pin layout of ICs usually does not correspond to the order of bus lines. We solved this problem by reserving a block of eight neighboring breadboard pin rows on both board halves where we connected all address lines in the correct bit order.
Testing
For testing, we used an Arduino Mega microcontroller that emulated the control lines, data bus and the address latch. We programmed the bootup ROM to contain a repeating pattern of values that are easy to verify knowing their addresses. Our test program then wrote data to a set of random locations withing the address space and afterwards read from all affected addresses. We expected the value to either be part of the pre-programmed ROM pattern if the location maps to the ROM, or to be the value written at the respective location. In later testing, we combined testing the memory and register units as described in the testing section of the register file documentation.